Switching mode power converters contribute to provide regulated voltages with relatively compact size and superior efficiency thereof. A switching mode power converter with direct-coupled topology, such as boost converter and buck converter, has its power output terminal directly coupled with the power input terminal through a power switch. Otherwise, a switching mode power converter with transformer-coupled topology, such as flyback converter and forward converter, has its power output terminal isolated from the power input terminal by a transformer, and the power switch is arranged at the primary side of the transformer. Pulse-width modulation (PWM) is a method employed by switching mode power converters to regulate their output voltages, by which the difference between the output voltage and a reference value is sensed to decide the duty cycle of the power switch in a switching mode power converter. A PWM power converter employs a PWM controller to provide a PWM signal with a constant frequency for a power stage, and the power stage includes a pair of high-side and low-side power switches alternately turned on by the PWM signal. The PWM controller also receives a feedback signal from the power stage in order to modulate the on-time of the high-side and low-side power switches, so as to convert an input voltage to an output voltage for supplying for a load.
There is some difficulty with using peak current mode control accurately, especially at light current levels. As a power switch turns on, circuit parasitics in the power stage, output rectifier reverse recovery characteristics and high current gate drive pulses can create significant noise pulses on the leading edge of the current sense signal. When the high-side power switch is on and the low-side power switch is off, the power input supplies a current to charge the output capacitor to thereby generate the output voltage. However, since the feedback signal received by the PWM controller is actually a current sense signal derived from the power stage, at the moment a huge current surges into the power stage, oscillation may happen at the leading edge of the current sense signal, resulting in leading-edge noise that adversely affects the stability of the system. Traditionally, this problem is solved by adding a small RC filter or a predetermined blanking pulse to filter or blank the leading edge noise from entering the feedback input of the PWM controller. The power converter is typically equipped with a LEB circuit, and a constant LEB time is defined in the system design, by which the current sense signal is disconnected when a clock is started till the LEB time is up, whereby the current sense signal is blocked from entering the PWM controller during the LEB time. Referring to FIG. 1, the LEB time represented by a dotted line is begun from the valley of the oscillator signal Ct, and introduces a LEB pulse window to blank the leading edge of the current sense signal so that the PWM controller will practice the feedback control according to the blanked current sense signal. At low operating frequency and high output current level, these techniques generally offer satisfactory results. However, at higher switching frequency, and almost always at lighter load, these techniques cannot deliver high power efficiency, even satisfactory line/load regulation.
The predetermined blanking pulse is set by a threshold and the RC constant which could vary due to process and temperature variations. As stated previously, this blanking period along with pulses generated by the oscillator, constitute the on-time of a PWM controller. While the beginning of the blanking period has no problems, the end of it is not. The end point of a blanking period might take a large portion of the PWM on-time, resulting in an on-time that is longer than desired. This will in turn pump up the output voltage, leading to bad line regulation. The output of the error amplifier would be lowered by the increase of the output voltage and the system would eventually enter the pulse skipping mode, which generally introduces large ripples as well as unwanted harmonics. Typically, as shown in FIG. 1, the valley of the oscillator signal Ct is the start point of the LEB time, and the end point has to be decided otherwise. For a power converter operating with low frequency, the end point of the LEB time is typically decided by the circuit designer during it is designed. Under consideration of the effects resulted from process variation and temperature drift, a circuit designer usually prefers to give a postponed end point for the LEB time so as to fully blank the leading-edge noise. This approach achieves good outcomes at low operating frequency and heavy load. However, with the operating frequency of the power converter higher and higher, a much longer LEB time is not only disadvantageous to high power efficiency but also adverse to good output/input regulation, for a power converter operating at high frequency and light load.
To solve the aforementioned problem, some approaches have been proposed to provide a variable LEB time. For example, in U.S. Pat. Nos. 6,144,245, 5,418,410 and 6,219,262, the gate current that the driver provides for the switching transistor is compared with a threshold, to decide the end point of a LEB time. However, due to the excessive prolongation, these approaches require some additional computations in order to decide the end point of the LEB time.